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8-bit, 40/80/100 msps dual a/d converter ad9288 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features dual 8-bit, 4 0 msps, 80 msps , and 1 00 msps adc low power: 90 mw at 100 ms ps per channel on-chip reference and track-a nd-hold 475 mh z analo g bandwidth e a ch channel snr = 47 db @ 41 mhz 1 v p-p an alog input range ea ch channel single 3.0 v su pply operation (2.7 v to 3.6 v) standby mode for single-channel operation twos complem e nt or offset binary ou tpu t mod e output data ali g nment mode pin-compatible 10-bit upgrad e avai lable applic ati o ns battery-powered instrum e nts hand-hel d scopemeters low cost digital oscilloscopes i and q commu nications func tio n a l block di agram 00585-001 ad9288 t/h ref t/h adc outp ut re gis t e r 8 8 8 8 outp ut re gis t e r timing timing v dd select 1 select 2 data format select d7 b ?d0 b d7 a ?d0 a v dd gnd v d enc a enc b a in a a in a a in b a in b ref in a ref out ref in b adc fi g u r e 1 . general description the ad9288 is a d u al 8-b i t m o n o li t h ic s a m p lin g a n alog-t o- dig i t a l con v er t e r wi t h o n -chi p t r ack-an d - h o ld c i r c ui ts. i t is o p t i m i ze d fo r lo w cost, lo w p o wer , sma l l size, a nd e a s e o f us e . the p r o d uc t o p era t es a t a 100 ms ps co n v ersion ra t e wi t h o u ts t a nding d y na mic p e r f o r ma n c e o v er i t s f u l l o p era t i n g ra n g e. e a ch cha n nel can b e o p er a t e d i n d e p e nden t ly . the ad c r e q u ir es o n l y a sin g le 3.0 v (2.7 v t o 3.6 v) p o w e r su p p ly a nd a n e n co de clo c k fo r f u l l -p er fo r m a n ce o p er a t ion. n o ext e r n al r e fer e nce o r dr i v er co m p on e n ts a r e r e q u ir e d fo r ma n y ap p l i c at i o n s . t h e d i g i t a l o u t p u t s a r e t t l / c m o s - c o m p a t i b l e , a nd a s e p a r a te ou t p ut p o w e r sup p ly p i n su pp o r ts in ter f aci n g wi th 3.3 v o r 2.5 v log i c. t h e en c o d e i n p u t i s t t l / c m o s - c o m pa ti b l e , a n d th e 8 - b i t dig i tal o u t p u t s c a n b e o p era t ed f r o m 3.0 v (2.5 v t o 3.6 v) suppl i e s . u s e r - s el e c t a bl e opt i on s of f e r a c o m b i n a t i o n of st an d b y m o d e s, di gi t a l da ta f o r m a t s, a n d d i gi tal d a ta t i mi n g sch e m e s. i n st and b y m o de, t h e dig i t a l o u t p uts a r e dr i v e n to a hig h im p e dan c e st a t e. f a b r ica t ed on an advan c ed cm os p r o c es s, t h e ad9288 is a v a i la b l e i n a 48 -le a d s u r f ace- mo un t plas t i c p a cka g e (7 mm 7 mm, 1.4 mm l q fp) s p e c if ie d o v er t h e i n d u st r i al t e m p era t ur e ra n g e (C40c t o +85c). th e ad9288 is p i n-com p a t i b le wi th th e 10 -b i t ad9 218, facili t a tin g f u t u r e sys t em mig r a t io n s .
ad9288 rev. c | page 2 of 24 table of contents specifications ..................................................................................... 3 explanation of test levels ........................................................... 4 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 test circ u its ..................................................................................... 12 ter mi nolo g y .................................................................................... 13 theory of operation ...................................................................... 14 using the ad9288 ...................................................................... 14 encode input ............................................................................... 14 digital outputs ........................................................................... 14 analog input ............................................................................... 14 volt age reference ....................................................................... 14 timing ......................................................................................... 14 user-selectable options ............................................................ 14 ad9218/ad9288 customer pcb bom ...................................... 15 evaluation board ............................................................................ 16 power connector ........................................................................ 16 analog inputs ............................................................................. 16 volt age reference ....................................................................... 16 clocking ....................................................................................... 16 data outputs ............................................................................... 16 data format/gain ...................................................................... 16 timing ......................................................................................... 16 troubleshooting .......................................................................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 12/04rev. b to rev. c change to absolute maximum ratings......................................... 7 replaced evaluation board section ............................................. 16 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 2/02rev. a to rev. b edits to absolute maximum ratings .............................. 3 1/01rev. 0 to rev. a 2/99revision 0: initial version
ad9288 rev. c | page 3 of 24 specifications v dd = 3.0 v; v d = 3.0 v, differential input; external reference, unless otherwise noted. table 1. test ad9288bst-100 ad9288bst-80 ad9288bst-40 parameter temp level min typ max min typ max min typ max unit resolution 8 8 8 bits dc accuracy differential nonlinearity 25c i 0.5 +1 .25 0.5 +1.25 0.5 +1.25 lsb full vi 1.50 1.50 1.50 lsb integral nonlinearity 25c i 0.50 +1.25 0.50 +1.25 0.50 +1.25 lsb full vi 1.50 1.50 1.50 lsb no missing codes full vi guaranteed guaranteed guaranteed gain error 1 25c i C6 2.5 +6 C6 2.5 +6 C6 2.5 +6 % fs full vi C8 +8 C8 +8 C8 +8 % fs gain tempco 1 full vi 80 80 80 ppm/c gain matching 25c v 1.5 1.5 1.5 % fs voltage matching 25c v 15 15 15 mv analog input input voltage range (with respect to a in ) full v 512 512 512 mv p-p common-mode voltage full v 0.3 vd 0.3 vd 0.3 vd 0.3 vd 0.3 vd 0.3 vd 0.3 vd 0.3 vd 0.3 vd v C0.2 +0.2 C0.2 +0.2 C0.2 +0.2 input offset voltage 25c i C35 10 +35 C35 10 +35 C35 10 +35 mv full vi C40 +40 C40 +40 C40 +40 mv reference voltage full vi 1.2 1.25 1. 3 1.2 1.25 1.3 1.2 1.25 1.3 v reference tempco full vi 130 130 130 ppm/c input resistance 25c i 7 10 13 7 10 13 7 10 13 k? full vi 5 16 5 16 5 16 input capacitance 25c v 2 2 2 pf analog bandwidth, full power 25c v 475 475 475 mhz switching performance maximum conversion rate full vi 100 80 40 msps minimum conversion rate 25c iv 1 1 1 msps encode pulse width high (t eh ) 25c iv 4.3 1000 5.0 1000 8.0 1000 ns encode pulse width low (t el ) 25c iv 4.3 1000 5.0 1000 8.0 1000 ns aperture delay (t a ) 25c v 300 300 300 ps aperture uncertainty (jitter) 25c v 5 5 5 ps rms output valid time (t v ) 2 full vi 2 3.0 2 3.0 2 3.0 ns output propagation delay (t pd ) 2 full vi 4.5 6.0 4.5 6.0 4.5 6.0 ns digital inputs logic 1 voltage full vi 2.0 2.0 2.0 v logic 0 voltage full vi 0.8 0.8 0.8 v logic 1 current full vi 1 1 1 a logic 0 current full vi 1 1 1 a input capacitance 25c v 2.0 2.0 2.0 pf digital outputs 3 logic 1 voltage full vi 2.45 2.45 2.45 v logic 0 voltage full vi 0.05 0.05 0.05 v power supply power dissipation 4 full vi 180 218 171 207 156 189 mw standby dissipation 4, 5 full vi 6 11 6 11 6 11 mw power supply rejection ratio (psrr) 25c i 8 20 8 20 8 20 mv/v
ad9288 rev. c | page 4 of 24 test ad9288bst-100 ad9288bst-80 ad9288bst-40 parameter temp level min typ max min typ max min typ max unit dynamic performance 6 transient response 25c v 2 2 2 ns overvoltage recovery time 25c v 2 2 2 ns signal-to-noise ratio (snr) (without harmonics) f in = 10.3 mhz 25c i 47.5 47.5 44 47.5 db fi n = 26 mhz 25c i 47.5 44 47 db f in = 41 mhz 25c i 44 47.0 db signal-to-noise ratio (sinad) (with harmonics) f in = 10.3 mhz 25c i 47 47 44 47 db f in = 26 mhz 25c i 47 44 47 db f in = 41 mhz 25c i 44 47 47 db effective number of bits f in = 10.3 mhz 25c i 7.5 7.5 7.0 7.5 bits f in = 26 mhz 25c i 7.5 7.0 7.5 bits f in = 41 mhz 25c i 7.0 7.5 7.5 bits second harmonic distortion f in = 10.3 mhz 25c i 70 70 55 70 dbc f in = 26 mhz 25c i 70 55 70 dbc f in = 41 mhz 25c i 55 70 70 dbc third harmonic distortion f in = 10.3 mhz 25c i 60 60 55 60 dbc f in = 26 mhz 25c i 60 55 60 dbc f in = 41 mhz 25c i 52 60 60 dbc two-tone intermod distortion (imd) f in = 10.3 mhz 25c v 60 60 60 dbc 1 gain error and gain temperature coefficient are based on the adc only (with a fixed 1.25 v external reference). 2 t v and t pd are measured from the 1.5 v level of the encode input to the 10%/90% levels of the digital outputs swing. the digital output l oad during test is not to exceed an ac load of 10 pf or a dc current of 40 a. 3 digital supply current based on v dd = 3.0 v output drive with < 10 pf lo ading under dynamic test conditions. 4 power dissipation measured unde r the following conditions: f s = 100 msps, analog input is C0.7 db fs, both channels in operation. 5 standby dissipation calculated with encode clock in operation. 6 snr/harmonics based on an analog in put voltage of C0.7 dbfs referenced to a 1.024 v full-scale input range. explanation of test levels level description i 100% production tested. ii 100% production tested at 25 c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by desi gn and characterization testing. v parameter is a typical value only. vi 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at tempera ture extremes for military devices.
ad9288 r e v. c | pa ge 5 o f 2 4 timing diagrams 00585-003 sample n sample n + 1 sample n + 2 sample n + 3 sample n + 4 sample n + 5 data n ? 4 data n ? 4 data n ? 3 data n ? 2 data n ? 1 data n data n + 1 a in a, a in b encode a, b d7 a ?d0 a d7 b ?d0 b data n ? 3 data n ? 2 data n ? 1 data n data n + 1 t eh 1/f s t el t a t pd t v f i g u re 2. n o r m al o p er at ion , s a me c l o c k (s1 = 1, s 2 = 0) c h ann e l ti m i ng 00585-004 sample n sample n + 1 sample n + 2 sample n + 3 sample n + 4 a in a, a in b encode a encode b d7 a ?d0 a d7 b ?d0 b t eh 1/f s t el t a t pd t v data n ? 7 data n ? 5 data n ? 3 data n ? 1 data n + 1 data n + 3 data n ? 8 data n ? 6 data n ? 4 data n ? 2 data n data n + 2 f i g u re 3. n o r m al o p er at ion w i t h t w o clo c k s o urc e s (s 1 = 1, s 2 = 0) cha nne l ti ming
ad9288 r e v. c | pa ge 6 o f 2 4 00585-005 sample n sample n + 1 sample n + 2 sample n + 3 sample n + 4 a in a, a in b encode a encode b d7 a ?d0 a d7 b ?d0 b data n ? 8 data n ? 6 data n ? 4 data n ? 2 data n data n + 2 data n ? 9 data n ? 7 data n ? 5 data n ? 3 data n ? 1 data n + 1 t eh 1/f s t el t a t pd t v f i g u re 4. d a t a a l ig n wit h t w o c l o c k s o urc e s (s1 = 1, s2 = 1) ch ann e l ti m i ng
ad9288 r e v. c | pa ge 7 o f 2 4 absolute maximum ratings table 2. p a r a m e t e r r a t i n g v d , v dd 4 v analog inputs C0.5 v to v d + 0.5 v digital inputs C0.5 v to v dd + 0.5 v vref in C0.5 v to v d + 0.5 v digital output c u rrent 20 ma operating tem p erature C55c to +125c storage temperature C65c to +150c maximum junction temperature 150c maximum case temperature 150c thermal imped a nce ja 57c/w s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions o u tside o f t h o s e i ndic a te d i n t h e op er a t ion s e c t io n s o f t h is sp e c if ic a t ion is n o t im pli e d . e x p o sur e t o a b s o l u te max i m u m ra t i n g s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad9288 r e v. c | pa ge 8 o f 2 4 pin conf iguration and fu nction descriptions 00585-002 gnd a in a v d en c b v dd gnd (ms b ) d7 b d6 b d5 b d4 b d3 b d2 b d1 b d0 b a in a dfs ref in a ref out ref in b s1 s2 a in b a in b gnd 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier nc nc v dd gnd gnd v d v d nc = no connect gnd gnd v dd nc nc ad9288 top view (not to scale) v d en c a v dd gnd d7 a (ms b ) d6 a d5 a d4 a d3 a d2 a d1 a d0 a f i gure 5. pin config ur ation table 3. pin no. name description 1, 12, 16, 27, 29, 32, 34, 45 gnd ground 2 a in a analog input for channel a. 3 a in a analog input for channel a (complementary). 4 dfs data format select. offset bina ry output available if set low. twos co mplement output available if set high. 5 ref in a reference voltage input for channel a. 6 ref ou t internal reference voltage. 7 ref in b reference volta g e input for channel b. 8 s1 user select 1. refer to table 4. tied with respect to v d . 9 s2 user select 2. refer to table 4. tied with respect to v d . 10 a in b analog input for channel b (complementary). 11 a in b analog input for channel b. 13, 30, 31, 48 v d analog supply (3 v). 14 enc b clock in put for channe l b. 15, 28, 33, 46 v dd digital supply (3 v). 17C24 d7 b Cd0 b digital output f o r channel b. 25, 26, 35, 36 nc do not connect. 37C44 d0 a Cd7 a digital output f o r channel a. 47 enc a clock input for channel a.
ad9288 r e v. c | pa ge 9 o f 2 4 typical perf orm ance cha r acte ristics 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 00585-006 sample db encode = 100msps a in = 10.3mhz snr = 48.52db sinad = 48.08db second harmonic = ? 62.54dbc third harmonic = ? 63.56dbc fi g u r e 6 . s p e c t r u m : f s = 100 msp s , f in = 10 mh z, s i ngl e -e n d ed input 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 00585-007 sample db encode = 100msps a in = 41mhz snr = 47.87db sinad = 46.27db second harmonic = ? 54.10dbc third harmonic = ? 55.46dbc fi g u r e 7 . s p e c t r u m : f s = 100 msp s , f in = 41 mh z, s i ngl e -e n d ed input 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 00585-008 sample db encode = 100msps a in = 76mhz snr = 47.1db sinad = 43.2db second harmonic = ? 52.2dbc third harmonic = ? 51.5dbc fi g u r e 8 . s p e c t r u m : f s = 100 msp s , f in = 76 mh z, s i ngl e -e n d ed input 72 68 40 0 1 02 0 3 04 05 06 07 08 09 0 44 48 52 56 60 64 00585-009 mhz db 2nd 3rd encode rate = 100msps f i gure 9. ha rm on ic d i s t o r ti on v s . a in fr e q u e n c y 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 00585-010 sample db encode = 100msps a in 1 = 9.3mhz a in 2 = 10.3mhz imd = ? 60.0dbc f i g u re 10. t w o - t o n e int e r m odu l at io n d i s t o r t i on 50 48 46 44 42 40 38 36 0 1 02 0 3 04 05 06 07 08 09 0 00585-011 mhz db encode rate = 100msps snr sinad f i gure 11. sinad/ s n r vs. a in fre q u e n c y
ad9288 rev. c | page 10 of 24 49 48 47 46 45 30 40 50 60 70 80 90 100 110 00585-012 msps db sinad snr a in = 10.3mhz f i gure 12. sinad/ s n r vs. enc o de rate sinad snr 50 46 38 42 34 30 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 00585-013 encode high pulse width (ns) db a in = 10.3mhz f i gure 13. sinad/ s n r vs. enc o de p u lse width high 0.5 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0 100 200 300 400 500 600 00585-014 bandwidth (mhz) db encode rate = 100msps ? 3db f i g u re 14. a d c f r e q uenc y r e s p ons e : f s = 100 msp s 190 185 180 175 170 165 160 155 150 145 140 0 100 90 80 70 60 50 40 30 20 10 00585-015 msps p o we r (mw) a in = 10.3mhz f i gure 15. a n a l og p o w e r d i s s i p a ti on v s . e n c o de ra te snr sinad 48.0 47.5 47.0 46.5 46.0 45.5 45.0 44.5 44.0 43.5 ?4 0 2 5 8 5 00585-016 temperature ( c) db encode rate = 100msps a in = 10.3mhz f i gure 16. sinad/ s n r vs. t e mper atur e 0.6 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 ?4 0 2 5 8 5 00585-017 temperature ( c) % gain encode rate = 100msps a in = 10.3mhz f i g u re 17. a d c g a i n v s . t e mper at ure ( w it h e x te rn al 1. 25 v r e f e r e nc e)
ad9288 rev. c | page 11 of 24 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 00585-018 code lsb f i gure 18. integ r a l non lin ea rit y 1.00 ? 1.00 ? 0.75 ? 0.50 ? 0.25 0 0.25 0.50 0.75 00585-019 code lsb f i g u re 19. d i f f e r e nt ia l n o nl in ea rit y 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 00585-020 load (ma) v re fout (v ) encode = 100msps v d = 3.0v t a = 25 c f i gure 20. v o ltage r e fer e n c e o u t v s . current l oad
ad9288 rev. c | page 12 of 24 test circuits 00585-021 a in a in 28k ? 12k ? 28k ? 12k ? v d f i g u re 21. equiv a le nt a n al og input c i rcuit 00585-022 v d v bias ref in f i gure 22. equiv a le nt refer e nc e input circuit 00585-023 encode v d f i gure 23. e q uiv a lent enc o de input circuit 00585-024 v dd out f i gure 24. equiv a le nt d i gital o u tput c i rcuit 00585-025 v d out f i gure 25. equiv a le nt refer e nc e o u tpu t circuit
ad9288 rev. c | page 13 of 24 terminology analog bandwidth (small signal) the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between a 50% crossing of encode and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential nonlinearity the deviation of any code from an ideal 1 lsb step. encode pulse width/duty cycle pulse width high is the minimum amount of time that the encode pulse should be left in logic 1 state to achieve rated performance; pulse width low is the minimum time encode pulse should be left in low state. at a given clock rate, these specs define an acceptable encode duty cycle. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between a 50% crossing of encode and the time when all output data bits are within valid logic levels. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. signal-to-noise ratio (snr) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered), or in dbfs (always related back to converter full scale). worst harmonic the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc.
ad9288 rev. c | page 14 of 24 theory of operation the ad9288 adc architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. these stages determine the 5 msbs and drive a 3-bit flash. each stage provides sufficient overlap and error correction, allowing optimization of comparator accuracy. the input buffers are differential, and both sets of inputs are internally biased. this allows the most flexible use of ac or dc and differential or single-ended input modes. the output staging block aligns the data, carries out the error correction, and feeds the data to output buffers. the set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. there is no discernible difference in performance between the two channels. using the ad9288 good high speed design practices must be followed when using the ad9288. to obtain maximum benefit, decoupling capacitors should be physically as close as possible to the chip, minimizing trace and via inductance between chip pins and capacitor (0603 surface-mount capacitors are used on the ad9288/pcb evaluation board). it is recommended to place a 0.1 f capacitor at each power-ground pin pair for high frequency decoupling, and to include one 10 f capacitor for local low frequency decoupling. the vref in pin should also be decoupled by a 0.1 f capacitor. it is also recommended to use a split power plane and a contiguous ground plane (see the evaluation board section). data output traces should be short (< 1 inch), minimizing on-chip noise at switching. encode input any high speed a/d converter is extremely sensitive to the quality of the sampling clock provided by the user. a track-and- hold circuit is essentially a mixer. any noise, distortion, or timing jitter on the clock is combined with the desired signal at the a/d output. for that reason, considerable care has been taken in the design of the encode (clock) input of the ad9288, and the user is advised to give commensurate thought to the clock source. the encode input is fully ttl/cmos-compatible. digital outputs the digital outputs are ttl/cmos-compatible for lower power consumption. during standby, the output buffers transition to a high impedance state. a data format selection option supports either twos complement (set high) or offset binary output (set low) formats. analog input the analog input to the ad9288 is a differential buffer. for best dynamic performance, impedance at a in and a in should match. special care was taken in the design of the analog input stage of the ad9288 to prevent damage and corruption of data when the input is overdriven. the nominal input range is 1.024 v p-p centered at v d 0.3. voltage reference a stable and accurate 1.25 v voltage reference is built into the ad9288 (ref out ). in normal operation, the internal reference is used by strapping pins 5 (ref in a) and 7 (ref in b) to pin 6 (refout). the input range can be adjusted by varying the reference voltage applied to the ad9288. no appreciable degradation in performance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage, which changes linearly. timing the ad9288 provides latched data outputs, with four pipeline delays. data outputs are available one propagation delay (t pd ) after the rising edge of the encode command (see figure 2, figure 3, and figure 4). the length of the output data lines and loads placed on them must be minimized to reduce transients within the ad9288. these transients can detract from the converters dynamic performance. the minimum guaranteed conversion rate of the ad9288 is 1 msps. at clock rates below 1 msps, dynamic performance degrades. typical power-up recovery time after standby mode is 15 clock cycles. user-selectable options two pins are available for a combination of operational modes. these options allow the user to place both channels, excluding the reference, into standby mode, or just the b channel. both modes place the output buffers and clock inputs into high impedance states. the other option allows the user to skew the b channel output data by 1/2 of a clock cycle. in other words, if two clocks are fed to the ad9288 and are 180 out of phase, enabling the data align allows channel b output data to be available at the rising edge of clock a. if the same encode clock is provided to both channels and the data align pin is enabled, then output data from channel b is 180 out of phase with respect to channel a. if the same encode clock is provided to both channels and the data align pin is disabled, both outputs are delivered on the same rising edge of the clock. table 4. user-selectable options s1 s2 option 0 0 standby both channels a and b. 0 1 standby channel b only. 1 0 normal operation (data align disabled). 1 1 data align enabled (data from both channels avail- able on rising edge of clock a. channel b data is delayed a 1/2 clock cycle).
ad9288 rev. c | page 15 of 24 ad9218/ad9288 customer pcb bom table 5. bill of materials no. qty. reference designator device package value comments 1 29 c1, c3-c15, c20, c21, c24, c25, c27, c30Cc35, c39Cc42 capacitor 0603 0.1 f 2 2 c2, c36 capacitor 0603 15 pf 8138 out 3 7 c16Cc19, c26, c37, c38 capacitor tajd 10 f 4 28 e1, e2, e3, e4, e12Ce30, e34Ce38 w-hole w-hole 5 4 h1, h2, h3, h4 mthole mthole 6 5 j1, j2, j3, j4, j5 sma sma j2, j3, not placed 7 3 p1, p4, p11 4-pin power connector post z5.531.3425.0 wieland 8 3 p1, p4, p11 4-pin power connector detachable connector 25.602.5453.0 wieland 9 1 p2, p3 1 80-pin rt. angle male tsw-140-08- l-d-ra samtec 10 4 r1, r2, r32, r34 resistor 0603 36 ? r1, r2, r32, r34, not placed 11 9 r3, r7, r11, r14, r22, r23, r24, r30, r51 resistor 0603 50 ? r11, r22, r23, r24, r30, r51 not placed 12 17 r4, r5, r8, r9, r10, r12, r13, r20, r33, r35, r36, r37, r40, r42, r43, r50, r53 resistor 0603 zero ? r43, r50 not placed 13 2 r6, r38 resistor 0603 25 ? r6, r38 not placed 14 6 r15, r16, r18, r26, r29, r31 resistor 0603 500 ? r16, r29 not placed 15 2 r17, r25 resistor 0603 525 ? 16 2 r19, r27 resistor 0603 4 k? 17 12 r21, r28, r39, r41, r44, r46Cr49, r52, r54, r55 resistor 0603 1 k? 18 2 t1, t2 transformer adt1-1wt minicircuits 19 1 u1 ad9288 2 lqfp48 20 2 u2, u3 74lcx821 21 2 u5, u6 sn74vcx86 22 4 u7, u8, u9, u10 resistor array cts 47 ? 768203470g 23 2 u11, u12 ad8138 op amp 3 1 p2, p3 are implemented as one physical 80-pin connector samt ec tsw-140-08-l-d-ra. 2 ad9288/pcb populated with ad9288-100. 3 to use optional amp: place r22, r23, r30, r24, r16, r29, remove r4, r36.
ad9288 rev. c | page 16 of 24 evaluation board the ad9218/ad9288 customer evaluation board offers an easy way to test the ad9218 or the ad9288. the compatible pinout of the two parts facilitates the use of one pcb for testing either part. the pcb requires power supplies, a clock source, and a filtered analog source for most adc testing required. power connector power is supplied to the board via a detachable 12-lead power strip. the minimum 3 v supplies required to run the board are v dd , v dl , and v dd . to allow the use of the optional amplifier path, 5 v supplies are required. analog inputs each channel has an independent analog path that uses a wideband transformer to drive the adc differentially from a single-ended sine source at the input smas. the transformer paths can be bypassed to allow the use of a dc-coupled path by using two ad8138 op amps with a simple board modification. the analog input should be band-pass filtered to remove any harmonics in the input signal and to minimize aliasing. voltage reference the ad9288 has an internal 1.25 v voltage reference; an external reference for each channel can be used instead by connecting two external voltage references at the power connector and setting jumpers at e18 and e19. the evaluation board is shipped configured for internal reference mode. clocking each channel can be clocked by a common clock input at sma input encode a/b. the channels can also be clocked independently by a simple board modification. the clock input should be a low jitter sine source for maximum performance. data outputs the data outputs are latched on-board by two 10-bit latches and drive an 8-pin connector which is compatible with the dual- channel fifo board available from analog devices. this board, together with adc analyzer software, can greatly simplify adc testing. data format/gain the dfs/gain pin can be biased fo r desired operation at the dfs jumper located at the s1, s2 jumpers. timing timing on each channel can be controlled if needed on the pcb. clock signals at the latches or the data ready signals that go to the output 80-pin connector can be inverted if required. jumpers also allow for biasing of pins s1 and s2 for power- down and timing alignment control.
ad9288 rev. c | page 17 of 24 00585-026 p6 p5 p7 v dd v d v dl + ++ + + + + c3 7 10 f c3 8 10 f c1 6 10 f c1 7 10 f c1 8 10 f c1 9 10 f c2 6 10 f gnd ?5v +5v v d v dd v dl v ref av ref b v dl v dd gnd v d 1 2 3 4 p1 v ref b v ref a gnd gnd 1 2 3 4 p4 gnd ?5 v +5v gnd 1 2 3 4 p11 h3 mthole6 h1 mthole6 h2 mthole6 h4 mthole6 gnd v d enc a v dd gnd d9 a (msb) d8 a d7 a d6 a d5 a d4 a d3 a d2 a c7 0. 1 f c8 0. 1 f gnd gnd d1 a d0 a gnd v dd gnd v d gnd v dd gnd d0 b d1 b c4 0. 1 f gnd c3 0. 1 f gnd c1 0. 1 f gnd d2 b d3 b d4 b d5 b d6 b d7 b d8 b (msb) d9 b gnd v dd enc b v d c5 0. 1 f c6 0. 1 f gnd gnd gnd amp o ut a amp o ut b amp o ut ab re f o ut gnd c1 0 0. 1 f c9 0. 1 f c1 1 0. 1 f c3 1 0. 1 f c1 4 0. 1 f r4 00 ? r5 00 ? r3 3 00 ? c1 5 0. 1 f c1 3 0. 1 f r3 5 00 ? r1 36 ? r2 36 ? r3 6 00 ? r3 4 36 ? r3 2 36 ? r6 25 ? gnd gnd gnd gnd gnd r3 50 ? gnd 1 2 6 5 gnd gnd 34 34 t2 1 2 6 5 j4 gnd amp i na amp i nb ain a j1 gnd ain b r3 8 25 ? r7 50 ? gnd e17 e18 e1 e19 e27 e30 e2 e25 vd vr efa e20 e24 e22 vd e29 gnd e23 e26 vd e28 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 gnd a in a a in a df s / gain re f in a re f out re f in b s1 s2 a in b a in b gnd 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 v d enc a v dd gnd d9 a d8 a d7 a d6 a d5 a d4 a d3 a d2 a ad9218/ad9288 u1 v d enc b v dd gnd d9 b d8 b d7 b d6 b d5 b d4 b d3 b d2 b d1 a d0 a gnd v dd gnd v d v d gnd v dd gnd d0 b d1 b gnd c1 2 0. 1 f gnd gnd gnd amp o ut bb r s i ngl e -e nde d r s i ngl e -e nde d r3 7 00 ? c3 0 0. 1 f c3 9 0. 1 f 2y 6 3a 9 gnd 7 3y 8 1a 1 1b 2 1y 3 2a 4 2b 5 vc c 4b 4a 4y 3b 14 13 12 11 10 e4 e3 e ncx a e ncx a e nca gnd gnd gnd gnd vd l ti ea vd l vd l cl kl at a gnd r3 9 1k ? r4 1 1k ? r1 1 50 ? c4 0 0. 1 f j3 gnd e ncode a vd l r4 4 1k ? r4 2 00 ? r4 3 00 ? c2 5 0. 1 f e13 e14 e12 vd l e15 gnd gnd r4 6 1k ? r4 7 1k ? r9 00 ? dra r1 0 00 ? u6 74lcx86 **dut cl ock s e l e c t abl e * * **t o be dire ct or buf f e re d** drb r1 2 00 ? 4b 13 1b 2 vc c 14 1a 1 3y 8 3a 9 3b 10 4y 11 4a 12 gnd 2y 2b 2a 1y 7 6 5 4 3 u5 74lcx86 e ncx b gnd vd l ti eb gnd r5 2 1k ? r5 4 1k ? r5 0 51 ? c4 2 0. 1 f j2 gnd e ncode b e ncx b e ncb r5 3 00 ? r5 0 00 ? e36 e35 gnd gnd gnd vd l vd l r4 9 1k ? c4 1 0. 1 f vd l e34 e37 e16 vd l e38 gnd gnd r4 8 1k ? r5 5 1k ? cl kl at b r1 3 00 ? **dut cl ock s e l e c t abl e * * **t o be dire ct or buf f e re d** j5 gnd r1 4 50 ? gnd r2 0 00 ? r4 0 00 ? ti ea ti eb en c a en c b r8 00 ? to ti e c l o c k s to g e th er gnd re f in b c2 4 0. 1 f gnd re f in a c2 7 0. 1 f t1 f i g u re 26. pcb s c h e m a t i c
ad9288 rev. c | page 18 of 24 00585-027 d9a 1 d8a 2 d7a 3 d6a 4 d5a 5 d9m d8m d7m d6m d5m 20 19 18 17 16 d4a 6 d3a 7 d2a 8 d1a 9 d0a 10 d4m d3m d2m d1m d0m 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 u7 cts20 value = 50 p3 header40 d9x 1 d8x 2 d7x 3 d6x 4 d5x 5 d9p d8p d7p d6p d5p 20 19 18 17 16 d4x 6 d3x 7 d2x 8 d1x 9 d0x 10 d4p d3p d2p d1p d0p 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 u9 cts20 value = 50 40 38 36 34 32 gnd dra gnd d9p d8p 39 37 35 33 31 30 28 26 24 22 d7p d6p d5p d4p d3p 29 27 25 23 21 20 18 16 14 12 d2p d1p d0p gnd gnd 19 17 15 13 11 10 8 6 4 gnd 2 gnd gnd gnd gnd gnd 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 d0m 11 gnd 12 d0x clklata 14 13 gnd 1 d9m 2 d8m 3 d7m 4 d6m 5 vdl d9x d8x d7x d6x 24 23 22 21 20 d5m 6 d4m 7 d3m 8 d2m 9 d1m 10 d5x d4x d3x d2x d1x 19 18 17 16 15 oe x0 x1 x2 x3 x4 x5 x6 x7 x8 vcc y0 y1 y2 y3 y4 y5 y6 y7 y8 x9 y9 gnd c l k u2 74lcx821 c21 0.1 f gnd +in 8 nc 7 v? 6 ?out 5 ?in vocm v+ +o u t 1 2 3 4 r16 525 ? r17 500 ? ad8138 ampouta ampoutab u11 ampina r18 500 ? r15 500 ? r19 4k ? r21 1k ? gnd gnd gnd +5 v +5 v c32 0.1 f c33 0.1 f r22 50 ? r23 50 ? ?5 v c2 15pf opamp input off pin one of transformer d0b 1 d1b 2 d2b 3 d3b 4 d4b 5 d0n d1n d2n d3n d4n 20 19 18 17 16 d5b 6 d6b 7 d7b 8 d8b 9 d9b 10 d5n d6n d7n d8n d9n 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 u8 cts20 value = 50 p2 header40 d0y 1 d1y 2 d2y 3 d3y 4 d4y 5 d0q d1q d2q d3q d4q 20 19 18 17 16 d5y 6 d6y 7 d7y 8 d8y 9 d9y 10 d5q d6q d7q d8q d9q 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 u10 cts20 value = 50 40 38 36 34 32 gnd drb gnd d9q d8q 39 37 35 33 31 30 28 26 24 22 d7q d6q d5q d4q d3q 29 27 25 23 21 20 18 16 14 12 d2q d1q d0q gnd gnd 19 17 15 13 11 10 8 6 4 gnd 2 gnd gnd gnd gnd gnd 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 d9n 11 gnd 12 d9y clklatb 14 13 gnd 1 d0n 2 d1n 3 d2n 4 d3n 5 vdl d0y d1y d2y d3y 24 23 22 21 20 d4n 6 d5n 7 d6n 8 d7n 9 d8n 10 d4y d5y d6y d7y d8y 19 18 17 16 15 oe x0 x1 x2 x3 x4 x5 x6 x7 x8 vcc y0 y1 y2 y3 y4 y5 y6 y7 y8 x9 y9 gnd c l k u3 74lcx821 c20 0.1 f gnd +in 8 nc 7 v? 6 ?out 5 ?in vocm v+ +o u t 1 2 3 4 r25 525 ? r29 500 ? ad8138 ampoutbb ampoutb u12 ampinb r26 500 ? r31 500 ? r27 4k ? r28 1k ? gnd gnd gnd +5 v +5 v c35 0.1 f c34 0.1 f r30 50 ? r24 50 ? ?5 v c36 15pf f i g u re 27. pcb s c h e m a t i c (cont i nu ed)
ad9288 rev. c | page 19 of 24 00585-028 f i g u re 28. t o p si lk s c r e en 00585-029 f i gure 2 9 . t o p ro ut i n g 00585-030 f i g u re 30. ground p l an e 00585-031 f i gure 31. spl i t p o w e r plan e 00585-032 f i gure 3 2 . bo ttom ro uti n g 00585- 033 f i g u re 33. bot t o m silk s c r e e n
ad9288 rev. c | page 20 of 24 troubleshooting if the board does not seem to be working correctly, try the following: ? ver if y p ower at t he ic pi ns. ? check that all jumpers are in the correct position for the desired mode of operation. ? ver if y t hat v ref is at 1.23 v. ? try running encode clock and analog inputs at low speeds (20 msps/1 mhz) and monitor lcx821 outputs, dac outputs, and adc outputs for toggling. the ad9218/ad9288 evaluation board is provided as a design example for customers of analog devices, inc. adi makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
ad9288 rev. c | page 21 of 24 outline dimensions top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc f i g u re 34. 4 8 -l ead l o w p r of i l e q u ad f l at p a ckag e [l qf p ] (st - 48) di me nsio ns sho w n i n mi ll im e t e r s ordering guide mode l t e mp er atur e ran ge packa g e des c r i pt ion packa g e o p ti on s ad9288bst-40 C40c to +85c 48-lead low profile quad flat package st-48 ad9288bstz-4 0 1 C40c to +85c 48-lead low profile quad flat package st-48 ad9288bstzrl - 40 1 C40c to +85c 48-lead low profile quad flat package st-48 ad9288bst-80 C40c to +85c 48-lead low profile quad flat package st-48 ad9288bstz-8 0 1 C40c to +85c 48-lead low profile quad flat package st-48 ad9288bst-10 0 C40c to +85c 48-lead low profile quad flat package st-48 ad9288bstz-1 0 0 1 C40c to +85c 48-lead low profile quad flat package st-48 ad9288 /pcb evalua tion boa r d 1 z = pb-free part.
ad9288 rev. c | page 22 of 24 notes
ad9288 rev. c | page 23 of 24 notes
ad9288 rev. c | page 24 of 24 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c00585C0 C 12/04(c)

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